There is an increasing interest in BiCMOS integrated circuit technologies (Bipolar+CMOS) for the performance of mixed function (i.e. analog and digital) functions within a single chip. Particular applications are frequently envisioned in the wireless marketplace. With the tremendous demand for f.sub.T improvement from the circuit design community, BiCMOS technologists still continue to scale down base width to increase NPN device performance. Unfortunately, scaling base width also lowers BV.sub.ceo, thus giving the device intolerable characteristics for 3.3 volt applications as well as manufacturing difficulties in the production line. Those concerned with the development of bipolar technology, in general and BiCMOS technology in particular have continuously sought improved in f.sub.T values as well as optimized base widths to yield desirable F.sub.t BV.sub.ceo products. Furthermore, it is desired to have a BiCMOS process with bipolar process modules which can be easily integrated into standard CMOS process modules.
FIG. 1 shows, by way of illustration, a typical conventional cross section of a BiCMOS integrated circuit 11. NPN transistor 19 is formed adjacent CMOS devices 13. Reference numeral 15 denotes a NMOS transistor, while reference numeral 17 denotes a PMOS transistor. Isolation oxides 31 serve to separate individual devices and tubs. For example, the p-tub is denoted by reference numeral 21, while the n-tub is denoted by reference numeral 23. NMOS device 15 is made within p-tub 21 and contains gate structure 27 with source and drain 53. PMOS device 17 is formed in n-tub 23 and contains gate 29 and source and drain 55 and 57. Buried layer 25 is formed beneath n+ tub 23. NPN transistor 19 is formed on top of buried n-tub layer 39. Transistor 19 includes an n+ sinker implant 41, polysilicon emitter structure 33, buried collector 39, emitter 61 and base 35. Region 37 is often termed the "selectively implanted collector." Typically, the fabrication process for the BiCMOS structure 11 begins with formation of a continuous buried layer including regions 25 and 39. Then, an epitaxial layer is formed on top of the buried layer and the appropriate dopings and tub definitions are performed.
Turning again to NPN transistor 19, it will be noted that the principal collector current conduction path is through selectively implanted collector 37, buried layer 39, and sinker 41. There is substantially less collector conduction through n-regions 63 and 67 because of their higher resistivity. (An appropriate collector contact is formed upon surface 43 although not shown.) Bipolar device 19 provides low collector resistance (Rc) and base-collector junction capacitance. However, the process utilized to form the device 11 of FIG. 1 is expensive and complex. It is difficult to integrate the formation of bipolar device 19 into the existing CMOS process modules which form CMOS pair 13 without changing the CMOS device characteristics.
Thus, those concerned with the development of bipolar technology in general, and BiCMOS technology in particular, have continuously sought bipolar devices with superior operating characteristics and have also sought bipolar devices which may be fabricated in the context of a CMOS process without undesirable side effects.